POSTER
Ryan Wong, Nabila Tasnim, Arjun Tyagi, Qingyuan Liu, Karan Annam, Saugata Ghose
Edge computing platforms are being employed for a wide range of use cases, but strict resource constraints can hamper the capabilities of such platforms. Particularly, as the machine learning model sizes and dataset footprints continue to grow, the inefficiencies of conventional computing hardware become intolerable for a range of edge applications (e.g., UAVs, XR, smart sensing). In recent years, there has been significant research on using in-memory computing (IMC; a.k.a. processing-using-memory) to deliver multi-order-of-magnitude improvements in ML inference. However, existing IMC approaches introduce a significant number of computation errors that, while tolerable for several uses of inference, are barriers to safety-critical applications and to in-the-field training.
We present a summary of work going on in the ARCANA Research Group at Illinois over the last year, where three separate research thrusts are working to overcome the reliability issues of IMC to make it practical for a much broader spectrum of edge applications. First, we are developing a new hybrid IMC architecture that combines analog IMC for inference with more error-resilient Boolean IMC operations. Second, we are developing a chip-scale architecture that uses new emerging memories (ECRAM) to enable in-the-field continual learning, with a focus on SLAM. Third, we are working with device-level experts to co-design error correction techniques that can bring IMC error rates closer to those of conventional CPUs.